1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device including a plurality of memory cells each having two storage regions.
2. Description of the Background Art
Among nonvolatile semiconductor memory devices, attention has been paid to an NROM (Nitride Read Only Memory) type flash EEPROM (to be referred to as xe2x80x9cNROMxe2x80x9d hereinafter) which is a kind of a flash EEPROM. NROM is described in U.S. Pat. Nos. 6,011,725 and 6,201,737.
FIG. 27 is a circuit diagram showing the configuration of the memory cell array of a conventional nonvolatile semiconductor memory device.
Referring to FIG. 27, the memory cell array includes a plurality of nonvolatile memory cells MC, a plurality of bit lines BL and a plurality of word lines WL.
A plurality of word lines WL and a plurality of bit lines BL are arranged in rows and columns, respectively.
Each nonvolatile memory cell MC is arranged to correspond to the intersection between word line WL and bit line BL. A plurality of nonvolatile memory cells MC arranged in the same row are connected in series and the gates thereof are connected to same word line WL. Each of bit line BL is arranged to pass through the connection point between two adjacent nonvolatile memory cells MC.
Nonvolatile memory cell MC has two storage regions L1 and L2.
Next, data write and read operations for writing and reading data to and from respective storage regions L1 and L2 of nonvolatile memory cell MC will be described.
FIGS. 28A to 28D show the data write and read operations for the two storage regions in a nonvolatile memory cell.
Referring to FIG. 28A, the gate of nonvolatile memory cell MC is connected to a word line WL. In addition, it is assumed that nonvolatile memory cell MC is connected to bit lines BL0 and BL1. Nonvolatile memory cell MC has storage region L1 on bit line BL0 side and, as shown in FIG. 28C, has storage region L2 on bit line BL1 side.
An operation for writing data to storage region L1 will first be described. Referring to FIG. 28A, if data is to be written to storage region L1, the potential of bit line BL0 is kept to be a write potential VCCW and that of bit line BL1 is kept to be a ground potential GND. As a result, a write current Ifw is carried from bit line BL0 to bit line BL1 through nonvolatile memory cell MC. At this moment, data is written to storage region L1. Such a write operation for writing data to storage region L1 in nonvolatile memory cell MC will be referred to as forward write.
Next, an operation for reading data from storage region L1 will be described. Referring to FIG. 28B, if data is to be read from storage region L1, the potential of bit line BL0 is kept to be ground potential GND and that of bit line BL1 is kept to be a read potential VCCR. As a result, a read current Ifr is carried from bit line BL1 to bit line BL0. At this moment, data is read from storage region L1. Such a read operation for reading data from storage region L1 in nonvolatile memory cell MC will be referred to as forward read.
As can be seen from the above, the direction of the current flowing in storage region L1 during the write operation is opposite to that of the current flowing in storage region L1 during the read operation.
A write operation for writing data to storage region L2 will next be described. Referring to FIG. 28C, if data is to be written to storage region L2, the potential of bit line BL0 is kept to be ground potential GND and that of bit line BL1 is kept to be write potential VCCW. As a result, a write current Irw is carried from bit line BL1 to bit line BL0. At this moment, data is written to storage region L2. Such a write operation for writing data to storage region L2 in nonvolatile memory cell MC will be referred to as reverse write.
Next, an operation for reading data from storage region L2 will be described. Referring to FIG. 28D, if data is to be read from storage region L2, the potential of bit line BL0 is kept to be read potential VCCR and that of bit line BL1 is kept to be ground potential GND. As a result, a read current Irr is carried from bit line BL0 to bit line BL1. At this moment, data is read from storage region L2. Such a read operation for reading data from storage region L2 in nonvolatile memory cell MC will be referred to as reverse read.
As can be seen from the above, the direction of the current flowing in storage region L2 during the write operation is opposite to that of the current flowing in storage region L2 during the read operation. Further, the direction of the current flowing during the write operation when the data is written to storage region L1 is opposite to that of the current when the data is written to storage region L2. Likewise, the direction of the current flowing during the write operation when the data is read from storage region L1 is opposite to that of the current when the data is read from storage region L2.
Consequently, it is important to control the potentials of respective bit lines BL in the write operation for NROM.
FIG. 29 is an explanatory view for the write operation for writing data to the nonvolatile memory cell in the memory cell array shown in FIG. 27.
Referring to FIG. 29, a case where H-level data is written to storage region L1 of a nonvolatile memory cell MC1 shown therein will be described.
A word line WL1 is selected, the potential of bit line BL0 is kept to be write voltage VCCW and that of bit line BL2 is kept to be ground potential GND. As a result, in nonvolatile memory cell MC1, write current Ifw is carried from a node connected to bit line BL1 to a node connected to bit line BL2. As a result, data is written to storage region L1. At this moment, when attention is paid to a nonvolatile memory cell MC0 adjacent nonvolatile memory cell MC1, an unnecessary current I1 is carried to nonvolatile memory cell MC0 if the potential of bit line BL0 is lower than that of bit line BL1. Unnecessary current I1 may possibly not only prevent power saving but also cause the memory cell array to malfunction.
Furthermore, according to the conventional art, data can be written to a memory cell of 1 bit at one time in the nonvolatile semiconductor memory device represented by NROM and throughput is thereby disadvantageously low.
It is an object of the present invention to provide a nonvolatile semiconductor memory device capable of suppressing a current which unnecessarily occurs during data write. It is another object of the present invention to provide a nonvolatile semiconductor memory device capable of improving throughput.
A nonvolatile semiconductor memory device according to the present invention includes: a plurality of word lines arranged in rows; a plurality of bit lines arranged in columns; a plurality of memory cells arranged in the rows and the columns; and a control circuit. Each of the plurality of memory cells has at least one storage region storing data. The control circuit selects a plurality of arranged continuously bit lines among the plurality of bit lines, and supplies a plurality of predetermined potentials corresponding to the selected plurality of bit lines. The plurality of memory cells arranged in the rows are connected in series and gates thereof are connected to the word line arranged in the row thereof, and each of the plurality of bit lines is connected to the plurality of memory cells arranged in the two adjacent columns.
As a result, even if the adjacent memory cells are connected to a common bit line, data write and read operations for one memory cell can be performed.
A nonvolatile semiconductor memory device according to the present invention includes: a plurality of word lines arranged in rows; a plurality of bit lines arranged in columns; a plurality of memory cells arranged in the rows and the columns; and a write circuit. Each of the plurality of memory cells has at least one storage region storing data. The write circuit writes a plurality of data to a plurality of continuously arranged memory cells among a plurality of memory cells arranged in the same row. The plurality of memory cells arranged in the rows are connected in series, and gates thereof are connected to the word line arranged in the row thereof, and each of the plurality of bit lines is connected to the plurality of memory cells arranged in the two adjacent columns.
As a result, this nonvolatile semiconductor memory device can write data to a plurality of continuously connected memory cells in one write operation. Throughput is thereby improved.
A nonvolatile semiconductor memory device according to the present invention includes: a plurality of word lines arranged in rows; a plurality of bit lines arranged in columns; a plurality of memory cells; and a write circuit. Each of the plurality of memory cells has at lest one storage region storing data and the plurality of memory cells are arranged in the rows and the columns. The write circuit writes a plurality of data to a plurality of continuously arranged memory cells among a plurality of memory cells arranged in the same row. The plurality of memory cells arranged in the rows are connected in series, and gates thereof are connected to the word line arranged in the row thereof, and each of the plurality of bit lines is connected to a plurality of memory cells arranged in the two adjacent columns. Each of the plurality of memory cells stores a plurality of data with not less than three levels.
As a result, the memory cells of this nonvolatile semiconductor memory device can store data of not less than three levels. Besides, this nonvolatile semiconductor memory device can write data to a plurality of memory cells in one write operation. Throughput is thereby improved.
The nonvolatile semiconductor memory device according to the present invention can select a plurality of bit lines and supply different potentials to the respective bit lines. Therefore, an unnecessary current generated during data write is suppressed. In addition, the nonvolatile semiconductor memory device according to the present invention can perform write and read operations to a plurality of memory cells. Throughput can be thereby improved.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.